In recent years, solid state drives (SSDs) have been developed as data storage apparatuses, each using NAND flash memories (hereinafter referred to as “flash memories” in some cases) that are rewritable nonvolatile memories.
Most SSDs are of a multichannel type, in which flash memories are managed in units of channels, and data is written to channels in parallel. In any SSD of the multichannel type, the data (user data) to be written in each channel is used, generating error correction codes (i.e., Reed-Solomon codes, hereinafter called “parity data” in some cases), which can perform interchannel parity (ICP) correction process. These error correction codes are stored in the flash memories of some channels selected from the plurality of channels.
In the SSD of the multichannel type, parity data capable of correcting data between the channels is generated and stored in the selected channels. Data to be stored in the flash memories may be managed in the SSD, in the form of logical blocks. The interchannel parity data is therefore allocated to given locations (storage locations) existing in the logical blocks. The method of allocating the interchannel parity data to storage locations may influence the SDD-mounting design, particularly the amounting design of the controller that accomplishes the interchannel parity (ICP) correction function.